The present invention relates to semiconductor devices and a method of fabricating the same and, more particularly, to semiconductor devices and a method of fabricating the same, which is capable of reducing the occurrence of bridges between metal lines.
With the higher integration of semiconductor circuits, Cu metal lines having low resistance are increasingly used as lines of the semiconductor circuits. However, a process of forming Cu lines cannot use a process of depositing a metal layer and then forming lines using photolithography and etching processes, which is applied to a conventional metal line formation process, due to the problems of dry etch. Accordingly, the process of forming Cu lines uses a damascene process of forming via hole or trenches, corresponding to line patterns, over a substrate, gap-filling the via holes or the trenches using an electro-plating process, and then etching Cu lines protruded over the substrate using a Chemical Mechanical Polishing (CMP) process.
As a pattern pitch recently becomes 100 nm or less, a bridge margin between Cu lines becomes short although a normal pattern profile is achieved. Bridges are caused because Cu residua, reacting to oxide at an interface after CMP, remain or Cu ions remaining in slurries at the time of CMP are absorbed by a patterned substrate again. Further, some scratches occurring at the time of CMP are all caused to generate bridges. At the current level of technology, in devices of 30 nm or less, Cu lines cannot be used due to the occurrence of bridges. Accordingly, there is an urgent need for this problem.